A 16-bit self-testing multiplier

A self-testing circuit is presented, i.e., a circuit able to signal out any inner fault. It is a 16-bit serial-parallel multiplier, based on a 2-bit Booth algorithm; data are coded in two's complement. The use of a rather cheap self-testing technique based on parity predicting results in the realization of a `self-testing-only' circuit requiring only about 25 percent extra silicon area. This realization permitted to study the feasibility of self-testing circuits. Critical points are also pointed out, such as the testing of I/O pins.