A system-oriented 5 V NMOS LSI circuit for data acquisition and front-end digital control

A 5 V n-channel enhancement/depletion circuit performs 8 bit data acquisition with a 5 V analog input range. It provides front-end digital control with adjustable set point and hysteresis. A simple constant-slope converter was developed, which is calibrated for a given application by tuning the built-in clock oscillator and adjusting the only reference, analog ground. For temperature compensation, the oscillator and the current source track with temperature. Digital subtraction was implemented with a three-decade synchronous BCD up/down counter, which produces positive or negative readings by a reversal of the counter. The circuit has a multiplexed three-digit TTL compatible BCD output. The chip size is 13 mm/SUP 2/ and it consumes 150 mW.