Modeling device and layout effects of performance driven I/sup 2/L

The performance of I/SUP 2/L gates at high injector current levels has been shown to be dependent on minority carrier charge storage and fan-out. These models, however, do not include the effects of extrinsic base resistance, parasitic diode shunting, and lateral p-n-p high level injection on the speed-power product curve. This paper considers these three factors with the aid of a device model, circuit simulations, and test data from logic race structures.