Design Guidelines for Oxide Semiconductor Gain Cell Memory on a Logic Platform

We offer design guidelines with a top–down and bottom–up design approach for oxide semiconductor (OS) transistors, optimized for gain cell memory on a logic platform. With high-density, high-bandwidth on-chip gain cell memory, deep neural network (DNN) accelerator execution times can be shortened by 51–66%, by minimizing access to off-chip dynamic random access memory (DRAM). To balance retention time with memory bandwidth (top–down), atomic layer deposition (ALD) indium tin oxide (ITO) transistors are chosen (bottom–up). The experimentally optimized device exhibits low off-state current (
$2\times 10^{-{18}}$
A/
$\mu \text{m}$
at
${V}_{\text {GS}}$
= -0.5 V), good on-state current (26.8
$\mu \text{A} / \mu \text{m}$
for power supply < 2 V), low subthreshold swing (SS) (70 mV/dec), and good mobility (27 cm2V-1s-1). Using this optimized device, a gain cell memory macro with 64 rows (WL)
$\times256$
columns (BL) is simulated at the 28 nm node operating at
${V}_{\text {DD}}$
= 0.9 V. The simulation results show that hybrid OS-Si gain cell memory achieves
$0.98\times $
frequency and
$3\times $
density of static random access memory (SRAM), and the OS-OS gain cell memory is projected to operate at
$0.5\times $
frequency with
${N}$
times
$1.15\times $
density of SRAM with
${N}$
-layer of 3-D stacking.