Design of a high-performance 1024-B switched capacitor p-channel IGFET memory chip

IGFET switched-capacitor memory cells are incorporated into a fully decoded dynamic, 1024-word by 1-b p-channel random-access memory. With 10-V drive circuitry, chip access time is measured to be 150 ns and cycle time is 300 ns. Measured on-chip power dissipation at a 300 ns cycle was less than 80 mW (80 /spl mu/W/b) and is correspondingly lower at lower speeds. Refresh power at 100/spl deg/C is less than 1 /spl mu/W/b.