A dynamic delay line with a bipolar one-transistor cell

A new bipolar one-transistor cell for the storage of analog information is described. This cell forms the basis of a 256-sample dynamic delay line, where 16/spl times/16 cells of a two-dimensional array are successively accessed. The circuitry for the generation of the selection voltages is specially designed in order to make the power dissipation independent of the size of the delay line.