Analysis of Nanosheet Field-Effect Transistor With Local Bottom Isolation

We propose a three-channel-based nanosheet field-effect transistor (BO NSFET3-channel) adopting a bottom isolation (BO) under inner gate regions to alleviate subleakage current as well as parasitic capacitance, simultaneously. To thoroughly evaluate the superiority of the proposed device, the conventional four-channel-based NSFETs were used with punchthrough stop (PTS) doping (NSFET4-channel) and BO scheme (BO NSFET4-channel) as references, and the electrical characteristics for each device were investigated using the 3-D technology computer-aided design (TCAD) simulations. For the proposed BO NSFET3-channel, although the PTS doping was not applied, it was observed that off-current and subthreshold swing (SS) characteristics are almost the same with the conventional NSFET4-channel with PTS doping because BO scheme can physically suppress direct source-to-drain leakage. It can also have less gate-induced drain leakage (GIDL) between the inner gate and substrate by BO scheme and small drain-to-substrate junction leakages by PTS doping skip. Furthermore, it was revealed that parasitic gate oxide capacitances are decreased about 9.03% compared to the references by adding the BO scheme under the inner gates, which hinders the bottom channel formation. As a result, it was confirmed that the intrinsic delay of the proposed device is improved 7.1% at
${I}_{{D}, \mathrm{OFF}}$
= 2 nA/
$\mu \text{m}$
compared to the conventional one. This proposed BO scheme would be beneficial for both n- and p-type NSFET devices and can provide valuable insights for the design of the next-generation logic devices.