Development of Wide-JFET Trench-Etched Double-Diffused MOS (TED-MOS) for High-Voltage Applications

We developed a modified trench-etched double-diffused MOS (TED-MOS) suitable for high-voltage devices that can be designed with a wide JFET to suppress JFET resistance. Our evaluation of the static and dynamic characteristics of modified TED-MOS chips showed that, compared to 3.3-kV double-diffused MOS (DMOS) chips, a lower
${\textit R}_{\text {on}}{A}$
even with a higher
${V}_{\text {th}}$
could be achieved. We also proposed a method to evaluate the potential of the device structure from the viewpoint of gate surge voltage and showed that the gate surge voltage of TED-MOS is smaller than that of DMOS with the same
${\textit dv}/{\textit dt}$
, which we attribute to the smaller
${C}_{\text {rss}}/{C}_{\text {iss}}$
. This feature is particularly effective for silicon carbide (SiC) devices that suffer from TDDB.