A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel for 3-D Integrated Devices

We have developed atomic layer deposition (ALD) process of InGaOx (IGO) and InSnOx for transistor channel and electrode and investigated the tradeoff among mobility, electrostatics, and reliability in single-gate (SG) IGO FETs. Threshold voltage (
${V}_{\text {th}}$
) shift after positive gate bias was observed especially in high Ga concentration and thin IGO channel devices, which can be attributed to excess oxygen. We also extracted interface and bulk state density (
${D}_{\text {it}}$
and
${N}_{\text {bulk}}$
) using the subthreshold swing (SS) measurement results from the channel thickness dependence.
${D}_{\text {it}}$
is as low as 1–
$2\times 10^{{11}}$
cm−2 eV−1, which means the formation of the defect-less interface between IGO channel and HfO2 gate dielectric. Ga concentration dependence of
${N}_{\text {bulk}}$
indicates the impact of O2 dimer generation in high Ga concentration devices. To break the characteristics tradeoff, we fabricated multigate nanosheet (NS) IGO FETs and demonstrated normally OFF operation, high mobility (>30 cm2/Vs), and high reliability. The drive current of the double-gate (DG) IGO FET is 2.2 times higher and the mobility is 1.2 times higher than that of the SG IGO FET, thanks to the multichannel structure and excess oxygen reduction by passivation process. The difference in positive bias instability (PBI) and negative bias instability (NBI) degradation between SG and DG structure was discussed by comparing the electric field distribution of TCAD simulation results of SG and DG IGO FET. This work shows the most well-balanced performance among preceding ALD IGO FETs with respect to mobility,
${V}_{\text {th}}$
, and SS, and shows the possibility of future 3-D back end of line (BEOL) monolithic and 3-D memory integration using ALD IGO channel.