Analysis of transconductances at all levels of inversion in deep submicron CMOS

This paper presents an in-depth analysis of transconductances in CMOS for advanced analog IC design. Transconductances in a 0.25 /spl mu/m CMOS technology have been measured over a large range of geometries and bias conditions. Gate (g/sub mg/), source (g/sub ms/), drain (g/sub md/) and bulk (g/sub mb/) transconductances are consistently normalized and represented vs. inversion coefficient (IC) from very weak to moderate and strong inversion. The ideal transconductance behavior in particular in weak inversion is analyzed via the analytical structure of the EKV MOSFET model. The new EKV 3.0 MOSFET model shows excellent abilities to correctly represent transconductances at all levels of inversion and channel lengths.