An 800 MHz 0.35 /spl mu/m CMOS clock tree and PLL based on a new charge-pump circuit

The paper presents the design of an 800 MHz PLL implemented in a 0.35 /spl mu/m CMOS technology. A novel charge pump circuit has been introduced in order to increase the frequency range of the PLL. A clock tree with buffers in the internal nodes has been designed for a chip of dimensions 1 cm/spl times/1 cm. The PLL supports internal to external clock frequency ratios of 1, 2, 4 and 8. PLL and clock tree have been used for power reduction by clock domain partitioning.