Impact of Sub-μm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era

Sub-
$\mu \text{m}$
wafer thicknesses are an essential enabler for the high-density nano through silicon via (nTSV) in design-technology co-optimization (DTCO) and system-technology co-optimization (STCO) scaling options. The measurement and TCAD results prove that decreasing the wafer thickness to 0.3
$\mu \text{m}$
is beneficial to latch-up prevention due to lower
$\beta $
-gain, which originates from the strong recombination in well-base regions. Moreover, the current flow for sub-
$\mu \text{m}$
Si thickness will be impacted and confined in a thinner bulk region. Additionally, the internal guard rings (GRs) efficiency increases by nearly 100% for
$0.3~\mu \text{m}$
Si thickness. On the contrary, the holding voltage is unchanged due to the dominant impact of increased well resistances over
$\beta $
-gain reduction. Also, the thermal impact on sub-
$\mu \text{m}$
Si thickness further increases latch-up risk due to reduced heat dissipation.