Modified Low-Voltage Triggered Silicon-Controlled Rectifier for ESD Protection

In this letter, a modified low-voltage triggered silicon-controlled rectifier (LVTSCR) is proposed and fabricated for electrostatic discharge (ESD) protection in a 0.18-
$\mu \text{m}$
1.8-V CMOS technology. The device leverages the parasitic p-n junction capacitance to detect ESD events, minimizing the need for additional detection elements. A PMOSFET is introduced to modulate the gate voltage of the NMOSFET in the MLVTSCR. By inserting diode-connected transistors into the trigger circuit and slightly enlarging the SCR path length, the holding voltage can be adjusted to a safe level. Experimental results indicate that the proposed MLVTSCR has a considerably smaller layout area than the widely used diode-triggered SCR, with comparable ESD robustness and leakage current.