A Passive Hybrid Circuit Model for Electrostatic Discharge (ESD) Characterization

Electrostatic discharge (ESD) is a critical factor affecting the reliability of advanced integrated circuit chips. Simulating device-level ESD in chips has become a challenging task due to the lack of a standardized physical model capable of characterizing a wide range of electrostatic stress conditions. This article introduces a novel passive hybrid ESD model, aiming to address this issue. The model greatly simplifies the calculation of nonlinear avalanche factor
${M}$
and improves its convergence properties. In particular, the proposed modeling method simplifies parameter extraction and reduces modeling complexity and can achieve the device electrical characterization of direct-current (dc) breakdown, transient clamping, and
${I}-{V}$
characteristics under different transmission line pulse (TLP) excitation conditions. We validated the effectiveness and accuracy of the proposed scheme using the 0.18-
$\mu \text{m}$
standard bipolar-CMOS-DMOS (BCD) process. The passive hybrid ESD model is a custom modeling approach mainly used to achieve simple device-level simulation and limited device characteristic evaluation. However, its co-simulation with large-scale circuits still has limitations. Furthermore, the aforementioned modeling approach is applicable to various types of ESD structures. By adjusting the key parameters of the model, it becomes possible to characterize device properties under different structures and sizes.