Impact of technology parameters on inverter delay of UTB-SOI CMOS

Ultra-thin-body silicon-on-insulator (UTB-SOI) is one of the most promising candidates for future CMOS technologies with minimum feature sizes below 50 nm. In this paper we analyse the impact of different parameters such as doping profile, gate work function and local interconnects on the inverter delay. For that purpose we have simulated fully-depleted (FD) SOI-MOSFETs with thin undoped silicon bodies using a coupled device and circuit simulation.