A reduced clock swing domino gate in SOI

The authors have introduced a domino gate that operates at a reduced clock swing. Using a DTMOS, the performance degradation is minimal while the total power consumption is greatly reduced since the clock tree has a halved voltage swing. Due to the squared relationship between voltage and power, 75% saving can be obtained on a clock whose contribution can be up to 50% of the overall power consumption. The use of active body-biasing circuits yields an order of magnitude reduction of the gate leakage power dissipation.