Optimizing a-IGZO Source-Gated Transistor Current by Structure Alteration via TCAD Simulation and Experiment

This study aims to increase the output current of the amorphous indium–gallium–zinc oxide (a-IGZO) source-gated transistor (SGT) through technology computer-aided design (TCAD) simulation and experiment. As SGT proves to be useful in various low-power applications and wearable devices, the low output current characteristics limit the adaptability of this structure. It is estimated that a higher output current level is achievable by optimizing this architecture while retaining fast saturation characteristics. The SGT structure simulations have been performed with adjusted density-of-states (DoS) parameters from experiments; this made TCAD simulation more realistic and can be used to predict the results of fabricated SGTs. The results from this study show that longer source–channel (SC) overlap and thinner channel is preferable; the SGT with longer SC overlap will result in the Mode II injection dominating over the Mode I injection. The Mode I injection occurs at the edge of source contact near the channel region, while the Mode II injection occurs at the bulk of the source at the farthest region from the channel. The result from the experiment shows that the fabricated SGT exhibits Mode II injection characteristics—that is the current will increase linearly with increasing gate voltage. From this study. it could be concluded that the SC overlap of
$210~\mu \text{m}$
with a channel thickness of 20 nm and a channel length of
$5~\mu \text{m}$
is the optimized structure that could provide high output current with little temperature dependence. Further improvement of the output current could be achieved by utilizing lower work function source metal.