A new staggered virtual ground array architecture implemented in a 4Mb CMOS EPROM

A new array architecture Is Introduced which Is suitable for very high density €PROMS. For a given set of design rules, this approach yields 40% Smaller array size compared to previous array architectures. The Staggered Virtual Ground (SVG) array has been Implemented based on the split gate EPROM technology. A dual function column muxing scheme and Address Transition Detection design techniques have been used to achieve a 90nS 4Mb EPROM. The die size Is 7.6mn x 6.5m and has been fabricated In a 1.25um CMOS technology.