A SOI CMOS Hall effect sensor architecture for high temperature applications (up to 300/spl deg/C)

The design of a 5 V fully integrated magnetic sensor able to operate up to 270/spl deg/C is presented. Fabricated in a Partially Depleted (PD) 1 /spl mu/m SOI process, this monolithic sensor comprises a resistive Hall plate, an amplifier stage and an A/D converter delivering a temperature stabilized 8-bit digital readout of the magnetic field. This circuit uses analog techniques for continuous compensation of temperature. Design issues inherent to partially depleted SOI, as well as constraints due to high temperature, are discussed.