A DC-4-GHz true logarithmic amplifier: theory and implementation

A 40 dB dynamic range, DC-4 GHz parallel-summation logarithmic amplifier is presented in this paper. The amplifier realizes a piecewise approximation to an exact logarithmic response. A design procedure that yields breakpoints on the exact response is described, along with delay-matching networks for parallel-summation logarithmic amplifiers. The amplifier was constructed in a 35 GHz silicon bipolar process, has /spl plusmn/5 dB logarithmic conformity over a DC-4 GHz bandwidth and has rise and fall times of 100 ps. The integrated circuit has dimensions of 2/spl times/2 mm/sup 2/ and consumes 750 mW from a -5 V supply.