Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low
$R_{\mathrm{ on,sp}}$
(Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length
${L}$
, field plate thickness
${H}$
, and slot contact width
${W}$
, have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that
$R_{\mathrm{ on,sp}}$
can achieve as low as 6.9m
$\Omega \cdot $
mm2 when the source-drain
${BV}$
(Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W
$=\,\,10~\mu \text{m}$
) and very large devices (W = 2mm).