A high performance function generator for multiplier-based arithmetic operations

An automatic hardware generator is developed for computing multiplier-based arithmetic functions. The generator can produce Verilog codes of parallel multipliers/multiplier-accumulator/inner product calculator and their corresponding test fixture files for pre-layout simulation. The irregular connection of the Wallace tree in the parallel multiplier is optimized in order to reduce the critical path delay. In addition to the conventional 3:2 counter that is usually included in standard cell library, our generator can select other different compression elements that are designed using the full-custom approach based on pass-transistor logic. Thus, our multiplier generator combines the advantages of three basic design methodologies: high-level synthesis, cell-based design, full-custom design along with area/time optimization.