Analysis and design of CMOS broadband amplifier with dual feedback loops

We present a broadband amplifier with 10.5dB gain and a 3dB bandwidth of 1.7GHz using CMOS 0.25/spl mu/m process in this paper. The technique of dual feedback loops was used in the amplifier for terminal impedance matching. Derived formulas for voltage gain (or S/sub 21/), input return loss(or S/sub 11/), output return loss (or S/sub 22/) as well as transimpedance gain with open load and 50 /spl Omega/ load (or Z/sub 21/ and Z/sub T/) have been used for the analysis and design of this amplifier. This circuit only dissipates 25 mW dc power.