Real-time segmentation architecture of gray-scale/color motion pictures and digital test-chip implementation

This paper proposes a digital algorithm for gray-scale/color image segmentation of real-time video signals and a cell-network-based implementation architecture in state-of-the-art CMOS technology. Through extrapolation of test-chip-data design in 0.35 /spl mu/m CMOS technology and simulation results we predict that about 50,000 /spl sim/ 100,000 pixels can be integrated on a chip in a 0.09 /spl mu/m CMOS technology, realizing very high-speed segmentation at about 300 /spl mu/sec per gray-scale/color image. Consequently real-time color-video segmentation will become possible in near future.