A 3.3 V-110 MHz 10-bit CMOS current-mode DAC

This paper describes a 3.3 V-110 MHz 10 bit CMOS current-mode digital to analog converter (DAC) weighting with a 6 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors (INL/DNL) caused by random and system errors are reduced by the proposed 2D hierarchically symmetrical centroid sequencing methodology. A new deglitch circuit is proposed to minimize the glitch energy. The simulation shows a conversion rate of 110 MHz, INI/DNL of /spl plusmn/0.8 LSB//spl plusmn/0.5 LSB, a glitch energy of 3.5 pV/spl middot/sec, and a power dissipation of 126 mW at 3.3 V.