Structure configuration of low power register file using energy model

This paper presents a transistor-level energy model of register files that using multi-port SRAM technology. Some register file circuit techniques are compared in energy efficiencies with the architectural parameters. According to the calculating and comparison results of energy model, structure configuration of register file is discussed from the point view of energy-efficiency. The realization of a 64/spl times/32 bits three-port register file proves register file with reasonable structure configuration has very low power and fast speed. Simulation results in a 2.5V 0.25 /spl mu/m CMOS technology show that the register file can operate at a 500 MHz frequency with 54 mW power dissipation.