A layout dependent and bias independent scalable substrate model for CMOS RF transistors

The dependence of the substrate resistance for MOS transistor RF modeling on biasing is studied from device simulations for a 0.5 /spl mu/m CMOS process. Though the substrate resistance is found to be bias dependent, the error incurred by assuming a constant value equal to the DC resistance is not significant. A scalable model for the substrate resistance of multiple gate fingers is developed. This model is simple to extract and gives good agreement for the output admittance.