A low-power digital matched filter for spread-spectrum systems

A digital matched filter (DMF) is an essential device for direct-sequence spread-spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for battery-powered terminals. The reception registers and the correlation-calculating unit dissipate the majority of the power in a DMF. In this paper we discuss this problem and propose a low-power architectural approach to a DMF. The total switching activity factor and the switched capacitance are reduced. As a result of power analysis at the gate level, the implementation of the proposed architecture in a standard 0.18-/spl mu/m CMOS technology achieved a reduction in the power consumption of more than 70%.