Using horizontal prefetching to circumvent the jump problem

The principle of a novel prefetching mechanism, horizontal demand prefetching, is presented. The mechanism allows deep prefetching without jump related misses by prefetching horizontally across independent instruction streams. The scheme can achieve high memory utilization at the expense of processor utilization. The mechanism permits very rapid context switching with no overhead for a hardware-limited number of tasks. The design and performance of a 16-b prototype machine is presented. The prototype exhibits a nonlinear relationship between the number of running streams and processor performance. This saturating performance-tasks relationship suggests that operations like process synchronization and interprocessor communication could be implemented very efficiently. Stalled streams need not greatly affect processor throughput.<
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