VLSI placement and area optimization using a genetic algorithm to breed normalized postfix expressions

We present a genetic algorithm (GA) that uses a slicing tree construction process for the placement and area optimization of soft modules in very large scale integration floorplan design. We have overcome the serious representational problems usually associated with encoding slicing floorplans into GAs and have obtained excellent (often optimal) results for module sets with up to 100 rectangles. The slicing tree construction process used by our GA to generate the floorplans has a runtime scaling of O(n lg n). This compares very favorably with other recent approaches based on nonslicing floorplans that require much longer runtimes. We demonstrate that our GA outperforms a simulated annealing implementation with the same representation and mutation operators as the GA.