Contrasting failure characteristics of different levels of Cu dual-damascene metallization

Currently, several kilometers of interconnects are used to construct a state-of-the-art Si-based integrated circuit, which has up to 8 levels of metallization. The failure mechanisms and reliability of the different layers of metallization are assumed to be the same in circuit-level reliability analysis. Although this may be true in Al interconnects, it may not be so for Cu dual-damascene lines. In this paper, we report on differences in the failure mechanisms between the first (M1) and second (M2) levels of Cu metallization, and how it affects the overall circuit reliability for Cu metallization.