Analysis of LDMOS structure with inclined p-bottom region

A new, 600V, RESURF LDMOS structure promising improvement on reliability, low on-resistance, and wide SOA region was proposed. The proposed LDMOS structure can reduce the electric field at silicon surface by about 40% using p-bottom layer for charge compensation without p-top layer. As carrier trapping into oxide at high electric field can be restrained, high reliability characteristics are expected. Most current flows around the silicon surface when the LDMOS turns on. However, in the proposed LDMOS, impact ionisation is repressed and current driving ability is increased by about 24%, voltage range is widened by 6% in SOA region because it has the low surface electric field. R/sub on,sp/ was improved by 15% when compared to the conventional LDMOS at the same breakdown voltage rating because there is no blocking layer in the drift region. This proposed LDMOS can also save one mask layer more than the conventional one.