A 150 K channelless gate array design in 0.5- mu m CMOS technology

The chip presented was designed as a vehicle to investigate the advantages and tradeoffs of using 0.5- mu m technology for semicustom VLSI devices. The use of 0.5- mu m technology requires that a 3.3-V supply be used. Several architectures were investigated for maximum efficiency and ease of use with place and route software, keeping in mind tradeoffs between routability, performance, and density. The problem of providing an adequate power distribution system that did not hinder array efficiency was addressed, and the provision of high-speed high-integrity clock signals to provide system speeds up to 100 MHz was a major consideration. The unique core cell, designed for this array to fully utilize the advantages of the technology, is discussed. System considerations such as synchronous data operations and testability were met by the inclusion of level-sensitive set-scan registers as an integral part of the I/O. Results highlight the observation that system performance is often limited by the device and interconnect parasitics, which have become increasingly more dominant with smaller geometries.<
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