Design integration, DFT, and verification methodology for an MPEG 1/2 audio layer 3 (MP3) SoC device

This paper describes the SoC design and integration methodology of a MPEG1/2 Audio Layer 3 (MP3) decoder chip. Due to a very tight development cycle we decided to use state of the art methodology for integration, verification, and design for test (DFT) in order to minimize risk and problem areas. The combination of a top-down integration flow, strong focus on constraint driven timing analysis, a modular simulation environment, and leading edge DFT solutions led to an implementation cycle of only 8 weeks. The chip is realized in an 0.18 /spl mu/m technology using 5 layers of metal, achieving a final die size of 16 mm/sup 2/. The central processor runs at a minimal speed of 140 MHz.