A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 /spl mu/m CMOS technology

In October 2000 the National Institute of Standard and Technology (NIST) chose the Rijndael algorithm as the new Advanced Encryption Standard (AES). In this paper we present an ASIC implementation of the Rijndael core. The core includes a non-pipelined encryption datapath with an on-the-fly key schedule data path. At a nominal 1.8 V, the IC runs at 125 MHz resulting in a throughput of 2.29 Gbit/s while consuming 56 mW. At 1.95 V, the chip can operate up to 154 MHz with an equivalent throughput of 2.8 Gbit/s and consumes 82 mW.