Experimental and simulation study of the effects of cosmic particles on CMOS/SOS RAMs

The existence of a charge multiplication effect in CMOS/SOS RAM circuits, as reported by J. Rollins (1987), is confirmed. Shorter channel lengths and higher power supply voltages caused the ratio, M, of upset charge to deposited charge to increase. As a result of this multiplication factor, actual devices are more likely to upset than expected from an analysis of only the collected charge. A mixed-mode simulator was used to model the charge collection process. The results showed that the M factor is a very fluid number which is dependent on minority carrier lifetime, drain voltage, and the switching dynamics of the cell in addition to the dependence on mobility ratio and channel length reported by Rollins. Parasitic bipolar gain at high injection levels appears to be the primary mechanism allowing collected charge to be greater than deposited charge. The simulator and experimental data show that, as floating body static memory transistors are down scaled, the particle energy needed to upset the cell is reduced because of the enhanced parasitic bipolar gain effect as well as a reduction in the node capacitance.<
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