A comparison of methods for total dose testing of bulk CMOS and CMOS/SOS devices

Low- and high-dose-rate testing results are compared for CMOS technologies. The long-term experiments extend over time periods of more than one year so that comparisons could be made over time frames more nearly like those in the space environment. High-temperature annealing is evaluated as a means of accelerating the annealing time and predicting low-dose-rate results. The data on hardened CMOS and CMOS/SOS devices show that for these particular processes, annealing at 100 degrees C did not accelerate trapped hole annealing. Differences between expected and actual results are identified, and recommendations are made for improving test procedures.<
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