A 3.3-V 18-bit digital audio Sigma-Delta modulator in 0.6-/spl mu/m CMOS

This paper presents a 3.3-V, 18-bit Sigma-Delta modulator for digital audio, which has been simulated in a 0.6 /spl mu/m double poly, triple metal CMOS process using poly-poly capacitors in all process corners and considering /spl plusmn/ 10 % power supply and -40/spl deg/C to 85/spl deg/C temperature ranges. The integral gain coefficients of a 2-2 cascaded modulator have been developed for achieving higher overload level factor that is needed for high-resolution noise limited performance modulators. Simulation results give SNDR of 111 dB and 110 dB in typical and worst case, respectively with considering of the circuit noise.