Low power finite field multiplication and division in re-configurable Reed-Solomon codec

Unlike most previous research on finite field arithmetic circuits, which focused on delay and area reduction, this work discusses the implementation for low-power. We describe finite field multiplier and divider circuits and their use in reconfigurable Reed-Solomon codec applications. We first analyze multiplier circuit switching activities with respect to input signal switching behavior. We then show that two multiplier inputs have asymmetric impact on the multiplier power dissipation. Using this important observation, we propose low power implementations of finite field multiplication and division for re-configurable Reed-Solomon codec applications. Our simulation results show that our implementation of finite field multiplication can reduce power by up to 40%. In addition, our proposed low power divider implementation achieves 15% power reduction. We have implemented several finite field multipliers and dividers in 0.18 /spl mu/m CMOS technology to examine our proposed low power technique. All designs are synthesized and operating at 100 MHz.