Efficient digit-serial normal basis multipliers over GF(2/sup m/)

In this article, two efficient architectures for digit-serial normal basis (DSNB) multipliers over GF(2/sup m/) are presented. These two structures have the same gate count and time complexity. A straightforward implementation leaves gate redundancy in both of them. An algorithm which can considerably reduce the redundancy is also developed. Moreover, the proposed architectures are compared with the existing ones in terms of gate and time complexities.