Current-sensing completion detection method for standard cell based digital system design

This paper shows how the current-sensing completion detection (CSCD) method can be applied for standard cell based digital system design. With the proposed method, conventional synchronous CMOS logic circuit blocks can easily be modified for self-timed asynchronous operation. To illustrate the usage of the method a self-timed CSCD multiplier-accumulator (MAC) was constructed. Simulation results and VHDL synthesized layouts of the CSCD MAC show that the CSCD method and the various proposed design practices can be used for the construction of self-timed asynchronous logic systems.