Design tradeoffs of CMOS current mirrors using one-equation for all-region model

The design of current mirror involves different conflicting design specifications (noise, bandwidth, input and output resistances, power dissipation, accuracy, THD, etc..), while only three design transistor parameters are available (DC current, width, length). In this paper, we address the effect of such parameters on the current mirror performance. For each specification, an expression is derived which is valid for any inversion level based on the one-equation for all-region MOS model. Experimental results from a current mirror fabricated in 0.5/spl mu/m AMI CMOS process are found in good agreement with the theoretical ones.