An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core

In this paper, we present a new architecture for a two-dimensional (2D) inverse discrete cosine transform (IDCT) core based on a modified radix-4 on-line CORDIC algorithm and distributed arithmetic (DA). The architecture is designed to take advantage of the "carry-free" addition property of redundant number representation and the "multiplierless" property of DA. The core operates on blocks of 8/spl times/8 pixels, with 12-bit and 9-bit precision for inputs and outputs, respectively. The proposed design is implemented on Xilinx Virtex XC2V 1000 FPGA. The test results show that the core for IDCT can operate at 100 MHz, while meeting the accuracy requirements of the CCITT H.26x standard.