Hierarchical compact models for simulation of electronic chip packages

Compact models are increasingly being used to represent chip packages in board and system-level computational fluid dynamics (CFD) simulations of electronics cooling. Thus far, the compact models used are relatively simple network analogs with network connectivity being determined by the designer's understanding of the underlying heat flow paths. Increasing the complexity of such models is difficult and must be done manually. In this paper, a methodology called COBRA (coefficient-based resistance agglomeration) is developed for automatically creating hierarchical compact models of increasing complexity. The technique creates a resistance network with automatically created network nodes which optimally represent the thermal distribution of the package. The method is based on automatic agglomeration of an underlying CFD mesh based on coefficient strength, and leads to network connectivities which reflect the heat flow paths dictated by the construction of the package. Network conductances are determined by minimizing the least-squares error between the predicted network nodal temperatures and data created either by detailed CFD simulations and/or experimental data. The computed conductances are used to predict temperatures at key locations in the chip package and are shown to perform satisfactorily.