A very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications

This paper presents a fully integrated low-voltage RF receiver frontend for 5-GHz radio applications, implemented in a standard 0.18 /spl mu/m CMOS technology. The receiver consists of a differential low noise amplifier, an active mixer, and a quadrature voltage-controlled oscillator. The complete receiver is packaged in a standard 24-pin ceramic flat pack (CFP) and consumes 56 mW from a 0.8-V supply. Measurement results show that the receiver has an overall noise figure of 7 dB and a -1 dBm input-referred third-order intercept point (IIP3).