Prediction of back-end process-induced wafer warpage and experimental verification

During the back-end processes of wafer manufacturing, wafer warpage occurs due to the mismatch in thermal expansion coefficients of the various applied materials. Large wafer warpage is one of the root causes leading to process and product failures. Therefore, the ability to predict the back-end process induced wafer warpage is important to achieve an optimal IC design and back-end process. This paper presents our research results of prediction and experimental verification of back-end process-induced wafer warpage due to thin film deposition and temperature changes. Both analytical and FE (finite element) methods are used to develop predictive models of the identified important back-end processes. These two models are verified by conducting warpage measurements of specially designed test wafers. Comparisons between the predictions with experimental results show that the predicted history of stress and warpage during the studied back-end processes are qualitatively reliable.