Consideration of chip circuit damage on DCS-FBGA packages

Laminate type FBGA package is one of the advanced solutions of economic chip scale package, effective for applications that require low profile and small area as cellular phones or hand held products. IBM stared to use an advanced package, DCS (Dual Chip Stacked)-FBGA, to obtain higher communication rate between dual semiconductor chips into one package, which were originally placed on different packages on wider space cards. During the development stage two subjects were concerned as, damage on the bottom-chip circuits under the top-chip placement region, and the reliability impacts. The top and bottom chip size combination in DCS-FBGA has a large difference ratio comparing to memory chips stack type packages, which is applied widely in the industry. Assessment studies on different CTE materials, chip thickness, construction, attachment methods, and reliability performances were analyzed. The result was validated by experiments to monitor the contact resistance discrepancy on the chip. To minimize these impacts, we confirmed the correlation between chip attach technique and mechanical reliability. This paper contains details of the phenomenon, solutions and effectiveness.