Dielectric Interface Engineering for High-Performance Monolayer MoS2 Transistors via TaOxInterfacial Layer

Field-effect transistors (FETs) based on 2-D materials have great potential for future ultimate-scaled electronics. However, nonideal semiconductor–dielectric interfaces due to interfacial traps and oxide traps have constrained the potential of 2-D semiconductors. Here, we report a new dielectric interface engineering approach for monolayer (1L) MoS2 transistors employing a relatively high-
$\kappa $
TaOx interfacial layer (
$\kappa \sim $
7) whose defect bands are located outside of the operation window of the MoS2 Fermi level. Such band alignment can minimize active interface trap states in top-gate (TG) dielectric stacks. The TaOx interfacial layer can also act as an efficient doping layer, with the highest ON-current
${I}_{\text {on}}$
reaching 861
$\mu \text{A}/\mu \text{m}$
at
${V}_{\text {DS}} $
= 1.5 V and overdrive voltage
${V}_{\text {OV}} $
= 3 V. The lowest contact resistance is down to
$230 \Omega \cdot \mu \text{m}$
. Dual-gate (DG) FETs can achieve subthreshold slope (SS) values down to
$\sim $
70 mV/dec in short-channel devices (
${L}_{\text {CH}} =55$
–75 nm). Our reported SS,
${I}_{\text {on}}$
, and
${R}_{C}$
are among the best-reported values for MoS2 devices. For low-power applications, our devices exhibit a record-high
${I}_{\text {on}}$
of 598
$\mu \text{A}/\mu \text{m}$
at
${V}_{\text {DS}} =0.65$
V. The new dielectric engineering approach proposed in this study can pave the way for realizing high-performance logic devices based on 2-D materials.