Analysis of a GaAs E-D inverter chain

Analytic formulas for the noise margins and pull-up and pull-down delays due to an input pulse with finite rise and fall times (rather than a step) of a GaAs enhancement-depletion (E-D) inverter and, by extension, of an inverter chain are derived. The formulas relate the DC and speed performance of an inverter to the current-voltage characteristics of the transistors, and indirectly to the device parameters. It is shown that for an inverter chain to be self-restoring, the logical-high and logical-low levels of the output voltage cannot be arbitrarily specified, that noise margins can be improved only logarithmically as the width ratios of the transistors are adjusted, and that the pull-up and pull-down delays are, to first order, proportional to the risetime of the input.<>