Gate-Controlled LVTSCR for High-Voltage ESD Protections in Advanced CMOS Processes

In this article, a novel high robust and latch-up immune electrostatic discharge (ESD) protection device, called gate-controlled low-voltage-triggered silicon-controlled rectifier (GC-LVTSCR), is proposed for 5-V I/O protection applications in the advance 40-nm CMOS technology. By incorporating a surface current diverting path with a controlling poly-silicon gate (CG) into the conventional LVTSCR, the GC-LVTSCR’s ESD characteristics can be improved and modulated with two bias conditions of CG. The first improved GC-LVTSCR structure named gate-to-body SCR (GBSCR) with the CG tied to the PWell’s body is expected to realize higher holding voltage (
${V}_{\text {h}}{)}$
and lower trigger voltage (
${V}_{\text {t1}})$
, while the other structure named gate-to-drain SCR (GDSCR) using the CG connected to the bridging p+ region of LVTSCR is designed to gain even higher
${V}_{\text {h}}$
. Measurement results show that the GBSCR has
$\sim $
11% lowered
${V}_{\text {t1}}$
,
$\sim $
38% enhanced
${V}_{\text {h}}$
, and improved charged device model (CDM) characteristics by comparing with the traditional LVTSCR, and the GDSCR possesses a further improved
${V}_{\text {h}}$
with
$\sim $
45% higher than the GBSCR. Besides, the new devices are expected to protect 5 V or above I/O in submicrometer technologies and have been realized in a 0.18-
$\mu \text{m}$
BCD process.